At-Speed BIST for Board-Level Interconnect

This article describes a novel Boundary Scan-like Built-In Self-Test (BIST) conception for autonomous at-speed testing and diagnosis of interconnect. It is based on recently proposed very efficient design of test pattern generation and response analysis hardware, which allows detection and diagnosis of both static and dynamic faults upon interconnects between chips in a multi-chip environment. The paper presents a system-level overview of the new testing paradigm and demonstrates its advantages over other known methods. It is shown that this paradigm brings a never achieved before high level of universality, scalability, and configuration independence into the at-speed interconnect testing and diagnosis of interconnect.